The present invention relates in general to semiconductor device fabrication methods and resulting structures. More specifically, the present invention relates to fabrication methods and resulting structures for a semiconductor device having a vertically integrated nanosheet fuse.
In contemporary semiconductor device fabrication processes a large number of semiconductor devices, such as field effect transistors (FETs) and electrically operable fuses, are fabricated on a single wafer. Electrically operable fuses are utilized in integrated circuits for a number of purposes, including the programming of alterable circuit connections, the replacement of defective circuit elements, and the storage of initial device configuration data. Electrically operable fuses are typically arranged in arrays, wherein each fuse array includes multiple fuses, and wherein each fuse in the fuse array can be individually selected and programmed. By activating a particular row and column of the fuse array, an individual fuse can be selected and programmed by providing a sufficient voltage across the fuse, thereby causing it to break down. The voltage at which a particular fuse will break down is known as the break down voltage.